1. Field of the Invention
The invention relates to a RAM store having a shared SA structure and to a control method for such a RAM store.
2. Background Information
In dynamic semiconductor memory chips (DRAMs), the bit line (BL) signals are assessed using sense amplifiers (SAs) that are connected to the right and left of a bit line pair. This “shared SA” design results in a surface-area-optimized sense amplifier array, which normally has half the repetition rate of the bit line pairs, in a sense amplifier strip situated between two adjacent cell blocks.
With reference to the appended FIGS. 1 and 2, a description is given of a known circuit arrangement for connecting two bit line pairs 11, 12, which each comprise complementary bit line halves (BLT, BLC), to a sense amplifier SA situated in a sense amplifier strip 10 between the cell blocks and of the circuit arrangement for charge equalization which is to be performed for the bit line halves BLT, BLC in a precharge phase and also of the aforementioned shared SA structure. First, FIG. 1 shows the arrangement of the control elements for a bit line pair 11, 12. An isolation transistor pair 1, 2 is turned on by a connection control signal (ISO) supplied via an Iso line 60 in order to connect a respective bit line pair to the sense amplifier SA. A charge equalization circuit has two drift equalization transistors 4, 5 and a shorting transistor 3. In response to a charge equalization signal EQL supplied via a control line 7, firstly the shorting transistor 3 shorts the two bit line halves BLT and BLC and secondly the drift equalization transistors connect the two bit line halves BLT and BLC to a predetermined center level Vcenter (local). This local center level Vcenter (local) is delivered by a voltage generator Vcenter (global) via a current limiter 6 and a supply line 8, whose purpose will be explained later.
As FIG. 2 shows, the circuit and control elements shown in FIG. 1 exist and can be controlled individually for each bit line pair. In this regard, the charge equalization control signals for the two bit line pairs 11 and 12 connected to the sense amplifier SA are respectively denoted by EQL1 (line 71) and EQL2 (line 72) in FIG. 2. Equally, the connection control signals for the left-hand bit line pair 11 and for the right-hand bit line pair 12 have the designations ISO1 and ISO2 (lines 61 and 62).
The center level Vcenter (local) on the supply lines 81 and 82 is the voltage which establishes itself after the spread or assessed bit line halves BLT, BLC have been shorted by the shorting transistor 3. The drift equalization transistors 4, 5 ensure that any leakage paths which may exist cause the center potential to be maintained on the two bit line halves BLT and BLC. Since the drift equalization transistors 4, 5 thus compensate merely for leakage currents, they are generally of significantly smaller design than the transistor 3 which shorts the bit line halves BLT, BLC. By contrast, the length of the precharge time is determined essentially by the shorting transistor 3 and hence by its size and current yield.
Reference is now made to the currently submitted patent application from the same applicant entitled “RAM-Speicher” [RAM store] (attorney's file 12366; official file reference not yet known), in which an SA uses four bit line pairs.
Such a shared SA design is shown schematically in the appended FIG. 3. As can be seen, the connection control signals (ISO1, ISO2, ISO3, ISO4) supplied to the isolation transistor pairs 1, 2 via the lines 61–64 can in this case connect four bit line pairs 11, 12 and 13, 14 to a sense amplifier SA. The circuit structure for the individual bit line pairs 11–14 can have the arrangement explained above as shown in FIG. 1. As can be seen, the control signals routed to the shorting transistors 3 and to the drift equalization transistors 4, 5 of the individual bit line pairs 11, 14 are denoted by EQL1–EQL4 (control lines 71–74) and the supply lines supplying the center level Vcenter are denoted by 81 and 82 in FIG. 3.
In addition, today's DRAM semiconductor memory chips have redundant memory elements which can replace faulty bit lines (or word lines) in order to optimize the efficiency of such DRAM semiconductor memory chips. Specifically in the case of bit line repair, today's repair designs are in a form such that one bit line pair (for example 11) associated with the sense amplifier can be repaired, that is to say replaced by a redundant bit line pair, by using this bit line address to access a redundant element in the same word line activation block, while the other bit line pairs, for example 12–14 associated with the same sense amplifier SA are used as previously.
If, by way of example, a bit line pair now has a short to a fixed potential (for example VSS) and is therefore replaced by an operational redundant bit line pair, this means that the further bit line pairs associated with the sense amplifier on which the replaced bit line pair, which is still shorted to VSS, is situated can be affected. Since the charge equalization activated in the precharge phase has every bit line, even repaired ones, connected to the same center level generator Vcenter (global), it is necessary to ensure that a bit line pair which is stuck at VSS (0 volt), for example, as a result of a short does not continue to load the center level generator Vcenter unnecessarily, or even influence its voltage, after it has been replaced by a redundant bit line pair. For this reason, as FIG. 1 shows, the current limiters 6 for each individual bit line repair unit are incorporated in the center level supply. The current limiters 6 thus generate the local center level Vcenter (local), which normally corresponds to the normal center level Vcenter (global), per bit line repair unit (for example a bit line pair). For the case of a faulty bit line, for example stuck at VSS, which has therefore been replaced, the current limiter 6 decouples the local center voltage Vcenter (local) from the global network and prevents the latter from being overloaded.
A problem arises with the normal DRAM semiconductor memory structure in that a bit line pair which is stuck at VSS and repaired affects the performance of the further, unrepaired bit line pairs linked to the same sense amplifier SA in another way during the precharge phase. In the precharge phase, despite the local center level for the faulty and intact bit line pairs being decoupled, the center level is influenced via the isolation transistors 1, 2, which are on in the precharge case. That is to say that the bit line pair (e.g. 11) originally at center level is connected via the isolation transistors associated with the two bit line pairs to the level of the faulty bit line pair, which unfortunately does not have the correct center level. Although the current limiter 6 for the intact bit line pair 11 prevents feedback to the center level network, all the further bit line pairs which are at the local center level Vcenter (local) of the intact bit line pair are influenced by the faulty bit line pair in the same way.
It will now be assumed that, in a subsequent phase, a memory cell situated on the intact bit line pair (for example 11) is selected by a word line. On account of the center level (which the faulty bit line has shifted toward VSS) on the intact bit line pair (for example 11), the signal swing for a memory cell which has been loaded with VSS (“0”) and is connected to the intact bit line pair 11 becomes increasingly smaller, and the correct recognition of the information in the memory cell by the sense amplifier is made more difficult. Similarly, the recognition of a “1” at a center level shifted toward VCC is made more difficult. In addition, the sense amplifier does not operate at its regular operating point, which can result in slower recognition of the information or in reduced sensitivity of the sense amplifier.